The present invention relates generally to a semiconductor manufacturing process, and more particularly to a method for formation of alignment features on a device.
During the manufacture of semiconductor devices, wafers undergo multiple photolithography steps. After an initial lithography operation, the wafers must be properly aligned in subsequent lithography operations such that the pattern exposed into the photoresist from previous lithography operations aligns properly. To accomplish this, most lithography tools utilize special alignment marks to align all subsequently patterned layers. These alignment marks are patterned by an exposure, without alignment, followed by an etch process, which transfers the resist pattern into the wafer silicon substrate. The alignment marks in the substrate must have an optimal depth, dependant upon the manufacturer of the pattern alignment system, to provide best quality contrast for the pattern alignment system. For example, step and scan alignment systems manufactured by ASML have an optimum depth of about 120 nm, while systems manufactured by others, e.g., Canon, Nikon, etc., have a different optimum depth.
Silicon-on-insulator (SOI) wafers are made of a composite structure consisting of an active layer of silicon deposited on insulating materials. The insulator, or dielectric, can be sapphire, silicon dioxide, silicon nitride, or other insulating form of silicon. Composition of a SOI wafer prior to processing typically consists of a stack of a thin upper silicon layer on top of a buried oxide (BOX) layer, which is above the support substrate silicon. Depending upon the device requirements, the thickness of the upper silicon layer may vary between 5 nm and 200 nm or more.
When the SOI upper layer is significantly thicker, e.g., 200 nm, than the desired alignment mark depth, e.g., 120 nm, the alignment marks can be formed in the upper silicon layer in a fashion similar to bulk wafer technology. If the SOI upper layer thickness is about the same as the desired (optimal) alignment mark depth, e.g., 100 nm, the alignment marks can be formed together with the trench isolation feature patterns. This situation has an advantage over bulk processing as the formation of the alignment marks and trenches occurs with a single lithography step and etch step, and is typically used in the manufacture of partially depleted SOI technology, as presented with reference to prior art FIGS. 1 through 3.
FIG. 1 illustrates a cross-sectional view of a portion of an SOI wafer 100 after pad oxide layer 18 growth, nitride layer 20 deposition, and photoresist masking 22 to form trench isolation feature opening locations 31 and alignment feature opening location 32. The other constituents of portion of SOI wafer 100 are SOI substrate silicon 12, a buried oxide layer (BOX) 14, and an SOI upper layer 16. Mask 22 serves to define the opening locations 31 and 32 for the trench isolation features and the alignment feature respectively by protecting the underlying portions during the etch process which follows, discussed with reference to FIG. 2.
FIG. 2 illustrates a cross-sectional view of SOI wafer portion 100 after an etch process to form the openings 33, i.e., trench isolation feature opening 33, and the opening 34, i.e., alignment feature opening 34. The trench isolation feature may be a shallow trench isolation (STI) feature. Photoresist mask 22 will be removed in subsequent processing steps. Because the thickness of SOI upper layer 16 is about the same as the desired (optimal) alignment mark depth, the alignment features 34 can be formed together with the trench isolation features 33 in a single etch step.
FIG. 3 illustrates portion of SOI wafer 100 after fill of openings 33 and 34 with a dielectric 24, such as silicon oxide, followed by planarization and removal of nitride and pad oxide layers. Alignment features 36 and trench features 35 have been patterned from upper SOI layer 16 in a single etch process. Planarization is typically accomplished by CMP (chemical mechanical polishing). SOI wafer portion 100 is ready for further fabrication processes toward device completion.
When the SOI upper layer thickness is significantly thinner than the desired alignment mark, as is typically the case in fully depleted SOI technology, it is impossible to use alignment marks in the upper SOI layer as was seen in FIGS. 1-3. This is because the marks would have insufficient contrast for the pattern alignment process. In this case, the alignment marks are formed in the bottom, support substrate silicon layer. To accomplish this, three separate lithography steps are required, as demonstrated with reference to prior art FIGS. 4 through 8.
FIG. 4 illustrates a cross-sectional view of a portion of an SOI wafer 200 after pad oxide layer 18 growth, nitride layer 20 deposition, and a first etch process wherein photoresist mask 22 serves to define an opening location 42 to define later placement of alignment features. Other constituents of portion of SOI wafer 200 are SOI substrate silicon 12, a buried oxide (BOX) layer 14, and an SOI upper layer 16. As before, mask 22 serves to protect the portions underlying mask 22 during the etching process. Opening location 42 is etched to the depth of the uppermost surface of the substrate 12, in preparation for the second photolithography process.
FIG. 5 illustrates the portion of wafer 200 after removal of the first resist layer and application of second resist mask 26. Second resist mask 26 serves to define an opening location 43 for subsequent etching into substrate 12. That is, photoresist mask 26 will be used to image the alignment features where the opening location (window) 42 was previously etched. In an embodiment, portions of layer 16 and 14, which remain after etching, will eventually serve as side walls for openings 50 (FIG. 7). Openings 50 shall serve as shallow trench isolation (STI) features in subsequent processing steps.
FIG. 6 illustrates a cross-sectional view of a portion 200 of an SOI wafer after etching into substrate 12. After completion of etch into substrate 12 to the desired depth, photoresist mask 26 is removed, in preparation for another lithography step and etch process.
FIG. 7 illustrates the portion 200 of SOI wafer after application of a STI pattern photoresist mask 27, and an etch process to form trench isolation feature openings 50, which serve to define shallow trench isolation features. This process uses the opening location 44 created in the previous etch process of FIG. 6 to properly align the STI mask 27. Mask 27 protects the formed location (alignment features) 44 during the etching process.
FIG. 8 illustrates the portion 200 of SOI wafer after fill of openings 50 and 44 with a dielectric, such as silicon oxide, followed by planarization and removal of nitride and pad oxide layers. Silicon oxide layer 54 has been patterned into upper SOI layer 16, while alignment features of the desired depth in formed opening 44 are patterned into substrate 12. As before, planarization of portion 200 is typically accomplished by CMP (chemical mechanical polishing). After planarization, SOI wafer portion 200 is subjected to further fabrication processes toward device completion.
To reach the point illustrated in FIG. 8 has required three lithography and etch processes, as discussed with reference to FIGS. 4 through 8. Thus the case where a thin SOI upper layer is used requires considerably more manufacturing capacity and cycle time than processing of SOI with a medium SOI top layer thickness, where only one lithography and etch step were needed. The thin SOI upper layer case also requires more manufacturing capacity and cycle time than the case of thick top layer of bulk material, in which only one lithography and etch steps are needed. However, in terms of device performance, it is desirable to use very thin SOI top layers, as thin SOI top layers enable formation of fully depleted SOI devices, e.g., devices that have lower leakage currents.
Therefore, what is needed is a method for forming alignment marks with the desired depth and STI features in thin upper SOI layers more efficiently than the current methodologies.